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--- sd:appendix_4_instruction_set_architecture [2026/03/30 11:25] – created appledog
+++ sd:appendix_4_instruction_set_architecture [2026/03/30 21:11] (current) – appledog
@@ Line 1: / Line 1: @@
 = Appendix 4 Instruction Set Architecture
 === Load/Store Instructions
 ^ Byte ^ Code ^ Example ^ Description |
 | 00 | LD_IMM   | LDA $5         | Load register with immediate value |
@@ Line 14: / Line 12: @@
 | 07 | ST_REG24 | STA [X:Y]      | Store A in memory using [low_byte:word] registers. |
 | 08 | ST_IMM24 | STA [$0:$A0]   | Store register in memory location [bank:addr] |
+<codify armasm>
+; ld/st example
+    LDA $1234        ; Load immediate $1234 into A
+    LDAL $42         ; Load immediate byte $42 into AL
+    LDA  [$F000]     ; Load word from address $F000
+    STA [2:$1000]    ; Store A to bank 2, offset $1000
+    STA [B:X]        ; Store into bank BL, offset X.
+    STA [BLX]        ; Store into bank BL, offset X.
+</codify>
+==== Assembly
+            LD_REG
+            A
+02         $201 (little endian)
 === Data Movement Instructions of the Caribbean
@@ Line 19: / Line 32: @@
 | 09   | MOV        | MOV Y, A                    | Copy A up on Y |
 | 0A   | XCHG       | XCHG X, Y                   | Swap dem two -- X an Y trade place, quick quick |
+==== Assembly
+00 01          MOV A, B
+A 02 03          XCHG X, Y
 === Pirate Stack Operations
@@ Line 52: / Line 69: @@
 === Logic Ops
-| 32   | AND                | AND dst, src          | Bitwise AND (compare two integers bit by bit) |
+|= Byte |= Instruction |= Example |= Description |= Flags Affected |
-| 33   | OR                 | OR dst, src           | Bitwise OR (same) |
+| 32   | AND                | AND dst, src          | Bitwise AND (compare two integers bit by bit) | |
-| 34   | XOR                | OR dst, src           | Bitwise XOR |
+| 33   | OR                 | OR dst, src           | Bitwise OR (same) | |
-| 35   | NOT                | NOT reg               | Invert all bits in an integer word |
+| 34   | XOR                | OR dst, src           | Bitwise XOR | |
-| 36   | TEST               | TEST dst, src         | Non-destructive AND |
+| 35   | NOT                | NOT reg               | Invert all bits in an integer word | |
-| 37   | AND_IMM            | AND dst, imm          | Bitwise AND with immediate |
+| 36   | TEST               | TEST dst, src         | Non-destructive AND | |
-| 38   | OR_IMM             | OR dst, imm           | Bitwise OR with immediate |
+| 37   | AND_IMM            | AND dst, imm          | Bitwise AND with immediate | |
+| 38   | OR_IMM             | OR dst, imm           | Bitwise OR with immediate | |
+=== Shift/Rotate Operations
+|= Byte |= Instruction |= Example |= Description |= Flags Affected |
+| 46   | SHL  | SHL A     | Shift left   | Z, N, C |
+| 47   | SHR  | SHR A     | Shift right  | Z, N, C |
+| 48   | SHLC | SHLC A    | Shift left   | Z, N, C |
+| 49   | SHRC | SHRC A    | Shift right  | Z, N, C |
+| 4A   | ROL  | ROL A     | Rotate left  | Z, N, C |
+| 4B   | ROR  | ROR A     | Rotate right | Z, N, C |
+| 4C   | ROLC | ROLC A    | Rotate left  | Z, N, C |
+| 4D   | RORC | RORC A    | Rotate right | Z, N, C |
+=== Comparison & Branching
+|= Byte |= Instruction |= Example |= Description |= Flags Affected |
+| 5A | CMP     | CMP A, B      | Compare (subtract, discard result) | Z, N, C, V |
+| 5B | CMP_IMM | CMP A, 0x0001 | Compare (subtract, discard result) | Z, N, C, V |
+| | JMP | | Unconditional jump  | None |
+| | JZ  | | Jump if zero        | None |
+| | JNZ | | Jump if not zero    | None |
+| | JC  | | Jump if carry set   | None |
+| | JNC | | Jump if carry clear | None |
+=== Subroutine Operations
+|= Byte |= Instruction |= Example |= Description |= Flags Affected |
+| | CALL | | Call subroutine (push IP, jump) | |
+| | RET  | | Return from subroutine (pop IP) | |
+| | INT  | | Software interrupt | |
+| | RTI  | | Return from Interrupt | |
+=== MMU/Block Operations
+| 8C | MEMCOPY  | | Return from Interrupt | |
+| 8D | SCAN  | SCAN H, N | Scan ptr H for needle N | |
+| 8E | CMPC3 | CMPC3 ELM, FLD, C | Compare Characters | Z C |
+=== Bit Packing
+| 98 | PAB | PAB | Pack low 4 bytes of A and low 4 bytes of B into AL | |
+| 99 | UAB | UAB | Unpack AL into low 4 bytes of AL and low 4 bytes of BL | |
+=== Flag Operations
+|= Byte |= Instruction |= Example |= Description |= Flags Affected |
+| A0 | SEZ     | SEZ | Set zero flag | Z |
+| A1 | SEN     | SEN | Set negative flag | N |
+| A2 | SEC     | SEC | Set carry flag | C |
+| A3 | SEV     | | Set overflow flag | V |
+| A4 | SEE     | | Set Extra Flag (User flag) | E |
+| A5 | SEF     | | Set Free Flag (User flag) | F |
+| A6 | SEB     | | Set Bonus Flag (User flag) | B |
+| A7 | SEU     | | Set User Flag (User flag) | U |
+| A8 | SED     | | Set Debug Flag | D |
+| A9 | SEI     | | Set Enable Interrupt | I |
+| AA | SSI     | | Enable Sound System Interrupts | S |
+| AB | CLZ     | | Clear zero flag | Z |
+| AC | CLN     | | Clear negative flag | N |
+| AD | CLC     | | Clear carry flag | C |
+| AE | CLV     | | Clear overflow flag | V |
+| AF | CLE     | CLE | Clear E | E |
+| B0 | CLF     | CLF | Clear F Flag (user flag)  | F |
+| B1 | CLB     |     | | B |
+| B2 | CLU     |     | | U |
+| B3 | CLD     |     | | D |
+| B4 | CLI     | CLI | Clear Interrupt Flag | I |
+| B5 | CSI     | CSI | Clear Sound Interrupt  | S |
+| B6 | SETF    | SETF 0x80     | Set bits in flags | * |
+| B7 | CLRF    | CLRF 0x80     | Clear bits in flags | * |
+| B8 | TESTF   | TESTF 0x80    | Non-destructive AND | Z C |
+=== Other
+|= Instruction |= Description |
+| TSX | Transfer SP to register* |
+| TXS | Transfer register to SP* |
+* (*) these opcodes were suggested by stackminer from the Fantasy Console 2.0 discord. Thank you, stackminer!
+=== System Operations
+|= Instruction |= Description |
+| YIELD | Poll UI, System Clock, Sound Chip, Video Chip, and others |
+| NOP | No operation |
+| HALT | Halt CPU (set H flag) |