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Appendix 4 Instruction Set Architecture

Byte	Code	Example	Description
00	LD_IMM	LDA $5	Load register with immediate value
01	LD_MEM	LDA [$5]	Load register from memory location
02	LD_REG	LDA [X]	load register from memory location
03	LD_REG24	LDA [X:Y]	Load register from memory location using [low_byte:word]
04	LD_IMM24	LDA [$1:$C000]	Load byte from memory location [bank:addr]
05	ST_MEM	STA [$10]	Store register in memory location
06	ST_REG	STA [X]	Store A in memory location using register as pointer
07	ST_REG24	STA [X:Y]	Store A in memory using [low_byte:word] registers.
08	ST_IMM24	STA [$0:$A0]	Store register in memory location [bank:addr]

Byte	Code	Example	Description
09	MOV	MOV Y, A	Copy A up on Y
0A	XCHG	XCHG X, Y	Swap dem two – X an Y trade place, quick quick

Byte	Code	Example	Description
0B	PUSH	PUSH A	Push A onto stack – ye scurvy dog!
0C	POP	POP Y	Pull stack value an' hand it over to register
0D	PUSHA	PUSHA	Save all registers in ye treasure chest
0E	POPA	POPA	Get the registers back
0F	PUSHF	PUSHF	Push “pirate” flags/status
10	POPF	POPF	Pop “pirate” flags back

Byte	Code	Example
15	INC	INC X
16	DEC	DEC Y

1E	ADD	ADD X, Y	Add X = X + Y
1F	SUB	SUB X, Y	Subtract X = X - Y
20	MUL	MUL X, Y	Multiply X:Y = X * Y (result may be 32-bit wide)
21	DIV	DIV X, Y
22	MOD	MOD X, Y
23	ADD_REG_IMM	ADD X, $1234
24	SUB_REG_IMM	SUB X, $ABCD
25	MUL_REG_IMM	MUL X, $100
26	DIV_REG_IMM	DIV X, $10
27	MOD_REG_IMM	MOD X, $FF
28	ADDC	ADDC X, Y
29	SUBC	SUBC X, Y
30	ADDC_REG_IMM	ADDC X, $5
31	SUBC_REG_IMM	SUBC X, $1

32	AND	AND dst, src	Bitwise AND (compare two integers bit by bit)
33	OR	OR dst, src	Bitwise OR (same)
34	XOR	OR dst, src	Bitwise XOR
35	NOT	NOT reg	Invert all bits in an integer word
36	TEST	TEST dst, src	Non-destructive AND
37	AND_IMM	AND dst, imm	Bitwise AND with immediate
38	OR_IMM	OR dst, imm	Bitwise OR with immediate

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