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Appendix 4 Instruction Set Architecture
Load/Store Instructions
| Byte | Code | Example | Description |
| 00 | LD_IMM | LDA $5 | Load register with immediate value |
| 01 | LD_MEM | LDA [$5] | Load register from memory location |
| 02 | LD_REG | LDA [X] | load register from memory location |
| 03 | LD_REG24 | LDA [X:Y] | Load register from memory location using [low_byte:word] |
| 04 | LD_IMM24 | LDA [$1:$C000] | Load byte from memory location [bank:addr] |
| 05 | ST_MEM | STA [$10] | Store register in memory location |
| 06 | ST_REG | STA [X] | Store A in memory location using register as pointer |
| 07 | ST_REG24 | STA [X:Y] | Store A in memory using [low_byte:word] registers. |
| 08 | ST_IMM24 | STA [$0:$A0] | Store register in memory location [bank:addr] |
; ld/st example
LDA $1234 ; Load immediate $1234 into A
LDAL $42 ; Load immediate byte $42 into AL
LDA [$F000] ; Load word from address $F000
STA [2:$1000] ; Store A to bank 2, offset $1000
STA [B:X] ; Store into bank BL, offset X.
STA [BLX] ; Store into bank BL, offset X.
Assembly
00 LD_REG
00 A
01 02 $201 (little endian)
Data Movement Instructions of the Caribbean
| Byte | Code | Example | Description |
| 09 | MOV | MOV Y, A | Copy A up on Y |
| 0A | XCHG | XCHG X, Y | Swap dem two – X an Y trade place, quick quick |
Assembly
09 00 01 MOV A, B
0A 02 03 XCHG X, Y
Pirate Stack Operations
| Byte | Code | Example | Description |
| 0B | PUSH | PUSH A | Push A onto stack – ye scurvy dog! |
| 0C | POP | POP Y | Pull stack value an' hand it over to register |
| 0D | PUSHA | PUSHA | Save all registers in ye treasure chest |
| 0E | POPA | POPA | Get the registers back |
| 0F | PUSHF | PUSHF | Push “pirate” flags/status |
| 10 | POPF | POPF | Pop “pirate” flags back |
Boring, Normal increment operations
| Byte | Code | Example |
| 15 | INC | INC X |
| 16 | DEC | DEC Y |
Arithmetic Operations
| 1E | ADD | ADD X, Y | Add X = X + Y |
| 1F | SUB | SUB X, Y | Subtract X = X - Y |
| 20 | MUL | MUL X, Y | Multiply X:Y = X * Y
(result may be 32-bit wide) |
| 21 | DIV | DIV X, Y | |
| 22 | MOD | MOD X, Y | |
| 23 | ADD_REG_IMM | ADD X, $1234 | |
| 24 | SUB_REG_IMM | SUB X, $ABCD | |
| 25 | MUL_REG_IMM | MUL X, $100 | |
| 26 | DIV_REG_IMM | DIV X, $10 | |
| 27 | MOD_REG_IMM | MOD X, $FF | |
| 28 | ADDC | ADDC X, Y | |
| 29 | SUBC | SUBC X, Y | |
| 30 | ADDC_REG_IMM | ADDC X, $5 | |
| 31 | SUBC_REG_IMM | SUBC X, $1 | |
Logic Ops
| Byte | Instruction | Example | Description | Flags Affected |
| 32 | AND | AND dst, src | Bitwise AND (compare two integers bit by bit) | |
| 33 | OR | OR dst, src | Bitwise OR (same) | |
| 34 | XOR | OR dst, src | Bitwise XOR | |
| 35 | NOT | NOT reg | Invert all bits in an integer word | |
| 36 | TEST | TEST dst, src | Non-destructive AND | |
| 37 | AND_IMM | AND dst, imm | Bitwise AND with immediate | |
| 38 | OR_IMM | OR dst, imm | Bitwise OR with immediate | |
Shift/Rotate Operations
| Byte | Instruction | Example | Description | Flags Affected |
| 46 | SHL | SHL A | Shift left | Z, N, C |
| 47 | SHR | SHR A | Shift right | Z, N, C |
| 48 | SHLC | SHLC A | Shift left | Z, N, C |
| 49 | SHRC | SHRC A | Shift right | Z, N, C |
| 4A | ROL | ROL A | Rotate left | Z, N, C |
| 4B | ROR | ROR A | Rotate right | Z, N, C |
| 4C | ROLC | ROLC A | Rotate left | Z, N, C |
| 4D | RORC | RORC A | Rotate right | Z, N, C |
Comparison & Branching
| Byte | Instruction | Example | Description | Flags Affected |
| 5A | CMP | CMP A, B | Compare (subtract, discard result) | Z, N, C, V |
| 5B | CMP_IMM | CMP A, 0x0001 | Compare (subtract, discard result) | Z, N, C, V |
| | JMP | | Unconditional jump | None |
| | JZ | | Jump if zero | None |
| | JNZ | | Jump if not zero | None |
| | JC | | Jump if carry set | None |
| | JNC | | Jump if carry clear | None |
Subroutine Operations
| Byte | Instruction | Example | Description | Flags Affected |
| | CALL | | Call subroutine (push IP, jump) | |
| | RET | | Return from subroutine (pop IP) | |
| | INT | | Software interrupt | |
| | RTI | | Return from Interrupt | |
Flag Operations
| Byte | Instruction | Example | Description | Flags Affected |
| A0 | SEZ | SEZ | Set zero flag | Z |
| A1 | SEN | SEN | Set negative flag | N |
| A2 | SEC | SEC | Set carry flag | C |
| A3 | SEV | | Set overflow flag | V |
| A4 | SEE | | Set Extra Flag (User flag) | E |
| A5 | SEF | | Set Free Flag (User flag) | F |
| A6 | SEB | | Set Bonus Flag (User flag) | B |
| A7 | SEU | | Set User Flag (User flag) | U |
| A8 | SED | | Set Debug Flag | D |
| A9 | SEI | | Set Enable Interrupt | I |
| AA | SSI | | Enable Sound System Interrupts | S |
| AB | CLZ | | Clear zero flag | Z |
| AC | CLN | | Clear negative flag | N |
| AD | CLC | | Clear carry flag | C |
| AE | CLV | | Clear overflow flag | V |
| AF | CLE | CLE | Clear E | E |
| B0 | CLF | CLF | Clear F Flag (user flag) | F |
| B1 | CLB | | | B |
| B2 | CLU | | | U |
| B3 | CLD | | | D |
| B4 | CLI | CLI | Clear Interrupt Flag | I |
| B5 | CSI | CSI | Clear Sound Interrupt | S |
| B6 | SETF | SETF 0x80 | Set bits in flags | * |
| B7 | CLRF | CLRF 0x80 | Clear bits in flags | * |
| B8 | TESTF | TESTF 0x80 | Non-destructive AND | Z C |
Other
| Instruction | Description |
| TSX | Transfer SP to register* |
| TXS | Transfer register to SP* |
System Operations
| Instruction | Description |
| YIELD | Poll UI, System Clock, Sound Chip, Video Chip, and others |
| NOP | No operation |
| HALT | Halt CPU (set H flag) |
